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? semiconductor components industries, llc, 2005 september, 2005 ? rev. 3 1 publication order number: ncp1212/d ncp1212 current mode pwm controller for both forward and flyback converters ncp1212 is a high performance current mode pwm controller specifically designed for off?line and dc?to?dc converter applications. the device requires very few external components and offers designer additional protection for better system reliability. the device features a trimmed oscillator for precise duty cycle control, accurate bandgap voltage reference, high gain error amplifier, current sensing comparator and a high current totem pole output gate driver that ideally drives the external power mosfet. additionally, the device has built?in programmable brownout detect and soft?start features to enhance system reliability. also, the 48%/82% selectable maximum turn on duty cycle control and external programmable switching frequency capabilities make this device an ideal controller for both forward and flyback configurations. this device is available in both pdip?8 and space saving soic?8 packages. features ? trimmed oscillator charge and discharge current for precise duty cycle control ? internal high accuracy bandgap voltage reference ? current mode operation up to 200 khz ? inherent feed forward compensation ? latching pwm for cycle?by?cycle current limiting ? high current totem pole output gate driver ? low startup and operating current ? internal undervoltage lockout with hysteresis ? internal leading edge blanking for current feedback ? direct interface with optocoupler for secondary sensing ? built?in soft?start function, programmable by external capacitor ? user programmable 48%/82% maximum duty cycle selection ? output overvoltage protection against open loop ? ac line brownout detect protection ? output overload protection irrespective of auxiliary voltage level ? pb?free packages are available typical applications ? atx pc power supply ? universal input wall mount adaptors ? crt monitor ? all flyback and forward smps systems marking diagram a = assembly location l, wl = wafer lot y, yy = year w, ww = work week = pb?free package g = pb?free package http://onsemi.com pdip?8 n suffix case 626 1 8 1 8 soic?8 dsuffix case 751 ncp1212 awl yywwg 1 8 device package shipping ? ordering information ncp1212dr2 soic?8 2500/tape & ree l ncp1212p pdip?8 50 units / rail ncp1212dr2g soic?8 (pb?free) 2500/tape & ree l ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specification s brochure, brd8011/d. n1212 alyw 1 8 ncp1212pg pdip?8 (pb?free) 50 units / rail 18 5 3 4 (top view) fb cs ss/dmax pin connections 7 6 2 vcc bok ct gnd drv
ncp1212 http://onsemi.com 2 ac input + ? f1 fuse x2 cap 02 13 rfi filter x2 cap br1 1 2 4 3 + c1 470 f/400 v r1 576 k r2 3.3 k c2 10 nf/1 kv d1 mur180 rsense 0.22/2 w d2 mbr3045 + c7 3300 f/ 10 v 5 v gnd t3 ic1 ncp1212 fb bok cs ct ss/dmax vcc drv gnd form standby smps auxiliary winding c4 1 nf c3 0.1 f c5 0.1 f pc817 4 3 ic2 1 2 r6 220 r5 100 c6 0.1 f u1 tl431 r8 300 figure 1. typical application circuit r3 36 k q1
ncp1212 http://onsemi.com 3 fb +5 v 3 r r 9 k + ? 8 a +5 v + ? 28 a + ? 0.5 v overload shutdown 300 ns leb cs + ? 1 v ovlo (25 v) uvlo (10 v) vref regulator 5 v + 15 v + ? +5 v 45 a sw2 + ? 1.21 v bok ct osc clock imax max. duty cycle 48% or 82% s d clk q ? + 3.2 v + ? s q q reset overload enable d clk q s q q r f/f totem pole drive ss/dmax vcc drv gnd ? figure 2. simplified functional block diagram ? + current limit ? + brownout detection ? + ? + ? + ? +
ncp1212 http://onsemi.com 4 pin function description 1 fb feedback input this pin detects voltage feedback from output, can be connected directly to the optocoupler collector pin. 2 bok brownout detect with hysteresis this is the inverting input of the brownout detect comparator. the brownout detect comparator has a detect threshold voltage of 1.21 v. this pin senses the voltage of the bulk capacitor through a resistor divider network to determine the brownout event. the hysteresis band is provided by a 45 a current flows out of this pin to the resistor network. 3 cs current sense input during output on?time of the power switch, this pin receives a voltage proportional to power switch current set by the current sensing resistor. the information is utilized to terminate output switch conduction by pwm action or overcurrent limit circuitry. 4 ct programmed oscillator frequency connecting a capacitor from ct pin to ground programs the internal oscillator frequency. the oscillator can operate up to 200 khz. 5 gnd ic ground ? 6 drv gate driver output this is a high current totem pole output. the pwm driving control is provided by this pin. the current and slew rate capability of this pin are suitable to drive a power mosfet. 7 vcc positive supply to ic this pin is the positive supply of the ic. the driver output gets disabled when the voltage becomes higher than 25 v and the operating range is between 10 v and 25 v. the startup voltage is set at 15 v. 8 ss/dmax soft?start time programming and maximum duty cycle selection this is a multi?function pin. soft?start effect is provided during startup with a capacitor connected to this pin. after soft?start period elapsed, the capacitor is used for timing control to determine output overload. if only a capacitor is connected to this pin, its final voltage is 4.3 v and maximum turn?on duty cycle dmax is set at 82%. connect a resistor in parallel with the capacitor can alter the final voltage of this pin. 48% dmax is selected if this pin stays at 2.1 v to 2.8 v after soft?start period. maximum ratings (t j = 25 c unless otherwise noted.) rating power supply voltage (pin 7) v cc ?0.3, 28 v input/output pins (pins 1, 2, 3, 4, 8) v io ?0.3, 6.5 v gate driver output pin (pin 6) v drv ?0.3, 14 v power dissipation and thermal characteristics thermal resistance, junction?to?air, pdip?8 version thermal resistance, junction?to?air, soic?8 version r j?a 100 178 c/w output current, source or sink i drv 1.0 a operating junction temperature range t j ?40 to +150 c operating ambient temperature range t a ?25 to +105 c storage temperature range t stg ?55 to +150 c esd capability, hbm (all pins except v cc pin) (note 1) ? 2.0 kv esd capability, machine model (all pins except v cc pin) (note 1) ? 200 v maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. 1. this device series contains esd protection and exceeds the following tests: human body model (hbm) 2.0 kv per jedec standard: jesd22?a114. machine model (mm) 200 v per jedec standard: jesd22?a115. 2. latchup current maximum rating: 150 ma per jedec standard: jesd78.
ncp1212 http://onsemi.com 5 electrical characteristics (for typical values t j = 25 c, dmax = 48%, for min/max values t j = ?25 c to +105 c, v cc = 16 v unless otherwise noted.) characteristic symbol min typ max unit oscillator section oscillation frequency, t j = 25 c (dmax = 48%, c t = 1.0 nf) f osc?48 81 90 99 khz oscillation frequency, t j = 25 c (dmax = 82%, c t = 1.0 nf) f osc?82 72 80 88 khz frequency change against supply voltage (v cc = 13 v to 25 v, t j = 25 c) f osc?v ? 0.02 ? % frequency change against temperature (v cc = 16 v, t j = ?25 c to 105 c) f osc?t ? 5.0 ? % current sense section maximum current sense input threshold v cs 0.96 1.0 1.16 v propagation delay (current sense to gate after leb blanking) t plh ? 150 200 ns leading edge blanking time t leb ? 300 ? ns soft?start section soft?start charge current i ss 5.0 8.0 11 a overload timing discharge current (note 3) i sd ?i ss 15 20 26 a 48% duty cycle selection input voltage threshold v d48 ? 2.5 ? v 82% duty cycle selection input voltage threshold v d82 ? 3.0 ? v gate driver section gate drive sink capability, v cc = 15 v, v drv = 1.0 v i ol ? 100 ? ma gate drive source capability, v cc = 15 v, v drv = 5.0 v (note 4) i oh ? 300 ? ma gate drive voltage (from 1.0 v to 11 v) rise time (c l = 1.0 nf, t j = 25 c) t r ? 25 50 ns gate drive voltage (from 11 v to 1.0 v) fall time (c l = 1.0 nf, t j = 25 c) t f ? 25 50 ns ic power supply section v cc startup threshold voltage vcc th 13.5 15 16.5 v v cc overvoltage lockout threshold vcc ovlo 22.5 25 27.5 v v cc undervoltage lockout threshold vcc uvlo 8.5 10 11.5 v power supply current, before startup (v cc = 12 v) i c1 ? 0.15 0.26 ma power supply current, operating i c2 ? 3.0 5.0 ma power supply current, shutdown (v cc = 15 v) i c3 ? 3.0 ? ma brownout detect section (bok) brownout input threshold voltage v bok 1.14 1.21 1.27 v brownout hysteresis current i bok 38 45 54 a maximum duty cycle section maximum duty cycle at soft?start pin voltage between 2.1 v and 2.8 v (2.1 v v dmax 2.8 v) dmax 48 47 48 50 % maximum duty cycle at soft?start pin voltage higher than 3.0 v (v dmax 3.0 v) dmax 82 79 82 88 % 3. i sd is an internal current source not accessible externally. 4. the output voltage is internally clamped by 13.5 v zener.
ncp1212 http://onsemi.com 6 typical characteristics ?25 53 27 1 f osc?48 , oscillator frequency (khz) 75 t j , junction temperature ( c) 95 t j , junction temperature ( c) 80 85 90 105 v cs , maximum current sense input threshold (v) 1.05 figure 3. oscillator frequency with 48% duty cycle vs. junction temperature figure 4. oscillator frequency with 82% duty cycle vs. junction temperature figure 5. frequency change against supply voltage vs. junction temperature figure 6. maximum current sense input threshold voltage vs. junction temperature t j , junction temperature ( c) figure 7. propagation delay vs. junction temperature t j , junction temperature ( c) figure 8. leading edge blanking time vs. junction temperature t j , junction temperature ( c) 1.15 0.9 1.2 79 70 50 100 60 80 90 0.1 0.04 f osc?v , frequency change (%) 0 0.12 t j , junction temperature ( c) 0.02 0.06 0.08 1.0 1.1 0.95 160 t plh , propagation delay (ns) 0 200 40 80 120 350 200 t leb , leading edge blanking time (ns) 100 400 150 250 300 f osc?82 , oscillator frequency (khz ) ?25 53 27 110 5 79 ?25 53 27 1 105 79 ?25 53 27 110 5 79 ?25 53 27 1 105 79 ?25 53 27 110 5 79 dmax = 48% c t = 1 nf v cc = 13v to 25v dmax = 82% c t = 1 nf
ncp1212 http://onsemi.com 7 ?25 53 27 1 i ss , soft?start charge current ( a) 6 t j , junction temperature ( c) 9 t j , junction temperature ( c) 7 7.5 8.5 105 r ol , output sink resistance ( ) 1 figure 9. soft?start charge current vs. junction temperature figure 10. overload timing discharge current vs. junction temperature figure 11. 82% duty cycle selection input voltage threshold vs. junction temperature figure 12. output sink resistance vs. junction temperature t j , junction temperature ( c) figure 13. gate drive source capability vs. junction temperature t j , junction temperature ( c) figure 14. gate drive sink capability vs. junction temperature t j , junction temperature ( c) 0.7 1.2 79 20 0 35 15 25 30 2 v s2 , 82% duty cycle selection input voltage threshold (v) 0 5 t j , junction temperature ( c) 1 3 4 0.9 1.1 0.8 300 i oh , gate drive source current (ma) 50 350 150 200 250 350 200 50 400 150 250 300 i sd? i ss , overload timing discharge current ( a) ?25 53 27 110 5 79 ?25 53 27 1 105 79 ?25 53 27 110 5 79 ?25 53 27 1 105 79 ?25 53 27 110 5 79 6.5 8 10 5 100 100 i ol , gate drive sink current (ma) v cc = 15 v 80 s pulsed load 120 hz rate v drv = 1v v drv = 1v v drv = 5v v drv = 5v v drv = 8v v cc = 15 v 80 s pulsed load 120 hz rate
ncp1212 http://onsemi.com 8 ?25 53 27 1 t r , gate drive voltage rise time (ns) 0 t j , junction temperature ( c) 50 t j , junction temperature ( c) 10 30 40 105 i bok , brownout hysteresis current ( a) 40 figure 15. gate drive voltage rise time vs. junction temperature figure 16. gate drive voltage fall time vs. junction temperature figure 17. brownout input threshold voltage vs. junction temperature figure 18. brownout hysteresis current vs. junction temperature t j , junction temperature ( c) figure 19. maximum duty cycle, dmax 48 vs. junction temperature t j , junction temperature ( c) figure 20. maximum duty cycle, dmax 82 vs. junction temperature t j , junction temperature ( c) 50 25 55 79 20 0 50 10 30 40 1.3 1.0 v bok , brownout input threshold voltage (v) 0.8 1.4 t j , junction temperature ( c) 0.9 1.1 1.2 35 45 30 55 dmax 48 , maximum duty cycle (%) 20 60 25 45 50 70 50 100 60 80 90 ?25 53 27 110 5 79 ?25 53 27 1 105 79 ?25 53 27 110 5 79 ?25 53 27 1 105 79 ?25 53 27 110 5 79 2.1v v dmax 2.8v v dmax 3v 20 t f , gate drive voltage fall time (ns ) dmax 82 , maximum duty cycle (%) 35 40 30
ncp1212 http://onsemi.com 9 ?25 53 27 1 vcc uvlo , v cc under voltage lockout threshold (v) 6 t j , junction temperature ( c) 12 t j , junction temperature ( c) 8 9 11 105 i c1 , power supply current before startup ( a) 150 figure 21. v cc under voltage lockout threshold vs. junction temperature figure 22. v cc overvoltage lockout threshold vs. junction temperature figure 23. v cc startup threshold voltage vs. junction temperature figure 24. power supply current startup vs. junction temperature t j , junction temperature ( c) figure 25. power supply operating current vs. junction temperature t j , junction temperature ( c) figure 26. power supply shutdown current vs. junction temperature t j , junction temperature ( c) 0 200 79 24 15 30 21 27 11 vcc th , v cc startup threshold voltage (v) 5 20 t j , junction temperature ( c) 8 14 17 100 50 i c2 , power supply operating current (ma) 0.0 5.0 2.0 3.0 4.0 2.5 1.0 4.0 2.0 3.0 3.5 ?25 53 27 110 5 79 ?25 53 27 1 105 79 ?25 53 27 110 5 79 ?25 53 27 1 105 79 ?25 53 27 110 5 79 7 10 18 1.0 1.5 i c3 , power supply shutdown current ( a) v cc = 12v v cc = 16v vcc ovlo , v cc overvoltage lockout threshold (v) v cc = 15v
ncp1212 http://onsemi.com 10 figure 27. rise time of gate drive waveform (c l = 1 nf) figure 28. fall time of gate drive waveform (c l = 1 nf) figure 29. supply current vs. supply voltage (duty cycle = 82% and output load = 1 nf) figure 30. supply current vs. supply voltage (duty cycle = 48% and output load = 1 nf) v cc , supply voltage (v) figure 31. switch frequency vs. c t pin capacitance c t , pin capacitance (pf) 0.5 i c2 , supply current (ma) ?0.5 4 v cc , supply voltage (v) 0 3 3.5 switching frequency (khz) 0 300 100 150 200 015 10 525 20 0 15 10 52 5 20 400 800 600 1200 1000 50 250 i c2 , supply current (ma) 2.5 2 1.5 1 0.5 ?0.5 4 0 3 3.5 2.5 2 1.5 1 ramp up to 24 v ramp down from 24 v ramp up to 24 v ramp down from 24 v 48% duty ?cycle 82% duty cycle
ncp1212 http://onsemi.com 11 detailed operating descriptions introduction the ncp1212 implements a standard current mode architecture where the switch?off time is dictated by the peak current setpoint. this device represents an ideal candidate where low external part?count is the key system requirement. additionally, the device provides extensive value?added functions, soft?start, brownout detect, etc., that can be applied to low?cost ac?dc adaptor applications. the ncp1212 incorporates all the necessary functions normally needed in uc384x based power supply systems: oscillator section, pwm latch section, current sense section, brownout detect protection, soft?start and maximum duty cycle selection. with all those functions, this device becomes a good alternative to uc384x that can help to improve both performance and system cost. also, the innovative maximum duty cycle selection feature allows the device applied to both forward and fly?back mode configurations. detailed functions of individual internal blocks are described in below and a simplified functional block diagram is shown in figure 2. oscillator section the oscillator frequency is programmed by the capacitor connected to c t pin. the capacitor is charged by a constant current source to 3.8 v and 2.5 v for 82% and 48% maximum duty cycle condition respectively. once the selected voltage is reached, c t is then dischar ged by another constant current source down to 1.0 v and this charging and discharging action will carry on perpetually. desirable switching frequency can be selected by choosing proper value of timing capacitor, c t . the c t pin waveform is shown in figure 32. figure 32. c t pin waveform for oscillator 3.8 v 2.5 v 1.0 v 48% 48% 82% pwm latch section ncp1212 works in current mode. the power switch current is converted to a positive voltage by inserting a sensing resistor r sense between the power switch source and the ground. the power switch peak current is compared with the level shifted control input voltage on a cycle?by?cycle basis. figure 27 illustrated the internal blocks of the function. the pwm latch is initialized by the oscillator set signal and is terminated by the current sense comparator when the current exceeds the value dictated by the control input or current limit level. the current sense comparator latch configuration used ensures that only a single pulse appears at the output during any given oscillator cycle. figure 33. pwm latch function fb +5 v 3 r r 9 k 300 ns leb s q q current limit + ? output + ? output + ? 1 v oscillator reset set r f/f drv cs 1 2 3 4 rsense pwm control totem pole driver
ncp1212 http://onsemi.com 12 current sense section the current sense pin, cs detects the voltage drop across a current sensing resistor, r sense connected in between the power mosfet and ground. in most cases, a narrow spike on the leading edge of the current waveform can be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. the spike is due to the power transformer inter?winding capacitance and output rectifier recovery time which are unavoidable. ncp1212 provides a 300 ns leading edge blanking block to shield off the spike. w ith the leading edge blanking function, the cs pin is not sensitive to the power switch turn?on noise and spikes, practically in most applications, no filtering network is required. in normal operation, voltage developed at the current sense input is compared with the level shifted control input voltage and an internal current limit threshold, v cs . in case the cs input exceeds the current limit threshold, which is 1.0 v (typ.) in ncp1212, the gate driver output will be forced to turn off immediately. thus the maximum allowable peak current is given by the following equation: i pk(max) 1v r sense soft?start and maximum duty selection ncp1212 includes an internal soft?start function to simplify designer?s job hence make this device easy to use. during the startup phase, a constant current source of 8.0 a flows out of the ss/dmax pin once v cc attains the minimum startup voltage. the capacitor connected at ss/dmax pin is slowly charged up and the voltage developed plus one diode drop, v sst is compared with the saw?tooth waveform, c t from the internal oscillator as shown in figure 34. whenever c t voltage is higher than v sst , gate driver output will be turned off. since v sst rises slowly and it controls the output duty gradually increases as shown in figure 35. the minimum c t voltage is at 1.0 v, hence there is no output before ss/dmax pin attains about 0.4 v (1.0 v?1 diode drop). soft?start block will have no effect to the pwm operation once v sst reaches 3.2 v. figure 34. soft?start operation s q q + ? f/f overload enable reset + ? 3.2 v from c t vsst +5 v 8 a shutdown ss/dmax ncp1212 duty cycle control c ss figure 35. output pulse duty cycle depends on the ss/dmax pin voltage v sst v drv c t
ncp1212 http://onsemi.com 13 ss/dmax pin is also used for the selection of maximum turn on duty cycle. the oscillator circuit is designed to operate in either 82% or 48% char ging time that corresponds to either 82% or 48% maximum pwm turn on duty cycle. as discussed in the oscillator section, saw?tooth waveform at c t pin is different for 82% and 48% maximum turn on duty cycle and it is shown in figure 32. the final voltage at ss/dmax pin determines the maximum turn on duty cycle. if 82% maximum turn on duty is desired, simply connect a capacitor from ss/dmax pin to ground as shown in figure 36 and the final voltage on the capacitor will be 5.0 v minus one diode drop ( 4.3 v). figure 36. 82% maximum duty cycle selection 5.0 v i ss = 0.8 a ss/dmax c ss final voltage 4.3 v 82% max. duty cycle for 48% maximum duty cycle selection, we need to adjust the final voltage at ss/dmax to lower than 3.2 v minus one diode drop ( 2.5 v). this can be achieved by connecting a resistor in parallel with c ss as shown in figure 37. the value of this parallel resistor is given by the equation in below: r duty 2.5 v 8 a figure 37. 48% maximum duty cycle connection 5.0 v i ss = 8 a ss/dmax c ss final voltage = 2.5 v r duty 48% max. duty cycle overload detection during output overload or short circuit condition, the pwm controller will pump as much energy as possible to the secondary side and the power only limited by the cycle?by?cycle current limit setting. components in the power supply circuit such as the power mosfet and output rectifier may be damaged by this continuous stress. theoretically, fly?back converter has inherent short circuit protection provided that the pwm controller is supplied by a fly?back auxiliary winding and it has uvlo function. unluckily, it is quite common that the supply will experience very high leaky voltage spike that prevents the v cc voltage to fall below uvlo level during short circuit. ncp1212 is equipped with an integrated overload detection mechanism, which is irrespective of auxiliary winding voltage level. overload shutdown is no longer bothered by leakage spike hence a reliable overload protection system can be easily constructed by ncp1212 for both forward and fly?back configuration. overload detection block is shown in figure 38. overload condition is signified by current sense voltage hitting the maximum allowable voltage, 1.0 v. to avoid false trigger that may happen during transient load changes, c ss starts to discharge by 20 a (i sd ?i ss ). if overload condition persists, v sst voltage level drops to 0.5 v and triggers the overload shutdown. overload shutdown is only enabled after the soft?start period . due to the overload detection mechanism, it is mandatory to connect a capacitor at the ss/dmax pin. otherwise overload shutdown may be triggered during startup phase.
ncp1212 http://onsemi.com 14 figure 38. overload detection block diagram 1 v q d s clk q d clk +5 v 8 a 28 a + ? + ? + ? ? + current limit from current sense + ? osc clock ct dmax max. duty cycle 48% or 82% + ? 3.2 v + ? q s q overload enable reset + ? + ? 0.5 v overload shutdown ss/dmax brownout protection ncp1212 has a built?in comparator for brownout detection as shown in figure 39. positive terminal of the comparator is connected to a +1.21 v bandgap reference. the ic is prohibited from switching until brownout detect pin exceeds 1.21 v. once the brownout detect threshold is exceeded, 45 a flows out of the pin and the voltage at this pin is further pushed up to provide hysteresis effect. the brownout voltage setting is determined by the potential divider formed with r upper and r lower . equations to calculate the resistors are shown below: r upper r lower (v bulk_h
v bulk_l ) 45 a r lower [1.21 v(v bulk_h
v bulk_l )] (45 a v bulk_h ) where v bulk_h and v bulk_l are the desired upper and lower bulk capacitor voltage for brownout detection.
ncp1212 http://onsemi.com 15 figure 39. brownout detect block diagram 1.21 v +5 v 45 a bok to bulk capacitor brownout shutdown r upper r lower + ? output + ? sw2 + ? internal 5.0 v regulator a low current 5.0 v regulator is available internally for the device operation and reference voltages generation. this voltage not accessible externally and is designed to operate with no external bypass capacitor. totem pole output driver ncp1212 contains a single totem pole output stage that was specifically designed for direct drive of power mosfets. it is capable of up to 300 ma peak drive current and has a typical rise time and fall time of 25 ns with 1.0 nf load. overvoltage protection and under voltage lockout ncp1212 starts operation once v cc reaches 15 v. overvoltage protection (ovp) will be triggered if v cc exceeds 25 v and on the other hand, under voltage lockout (uvlo) will take place if v cc drops below 10 v. ncp1212 continues to draw 3.0 ma typical after overload or overvoltage shutdown is triggered. if the startup resistance connected to v cc pin is large enough such that v cc voltage keeps on dropping after shutdown, ncp1212 will restart once v cc drops below uvlo threshold. if the fault condition persists, ncp1212 will enter hi?cup operation. in case system latchoff is required in fault conditions, a smaller startup resistance can be used to sustain the device operation. ncp1212 will remain in shutdown mode as long as v cc is maintained above uvlo threshold after fault is detected.
ncp1212 http://onsemi.com 16 application information and typical waveforms the ncp1212 is an ideal choice for next generation isolated fix switching frequency forward mode converters that only need few external components to complete the system. converting your existing application from using uc384x controllers to ncp1212 is easy and simple. in below is a description on how to determine external components v alue for a typical application example. for the schematic of the application, please refer to figure 1 in this data sheet. finding the external component values can be broken down into several steps as introduced below: 1. select the maximum duty cycle for forward mode operation and calculate the soft?start time. select the system, operate in forward mode with 82% maximum duty cycle. only a capacitor is required at ss/dmax pin and the soft?start time is determined by the capacitor, c ss . its value is given by the equation below: c ss i t ss v 1
v 2 where: i is an 8.0 a constant current source flow out of the ss/dmax pin; t ss is the required soft?start time; v 1 is the upper threshold voltage in the oscillator block and which is effectively controlling the pwm maximum duty cycle at gate driver output. soft?start block will have no effect to the pwm operation once ss/dmax pin voltage reaches this threshold. this threshold voltage is 2.5 v with 48% maximum duty cycle; v 2 is about 0.4 v (1.0 v minus one diode drop) which is the lower v oltage threshold for the pwm operation. there will be no pwm gate driver output before ss/dmax pin voltage attains this threshold. for example, the required soft?start time is 50 ms, the timing capacitor, c ss can be calculated as: c ss 8 a 50 ms 2.5 v
0.4 v 0.182 f in this case, a 0.22 f capacitor is used for this application and the soft?start time is calculated as 57.75 ms. the char ging waveform at ss/dmax pin is shown in figure 40 . from the captured waveform, the charge time from 0 v to 4.0 v is 1 15.2 ms and for the voltage charging up to 2.5 v, i.e. hitting the upper threshold voltage, the elapsed time is about 70 ms that matched with the theoretical calculation closely. figure 40. ss/dmax pin charging waveform 115.2 ms 4.0 v overload condition is signified by current sense input voltage hitting the maximum current sense threshold, v cs . to avoid false trigger that may happen during transient load change, c ss starts to discharge by an internal current source of 20 a, i sd ?i ss and the overload protection will only be issued until the voltage at ss/dmax pin falls below 0.5 v. the discharging time, t dis for 0.22 f soft?start capacitor is given by: t dis c ss (v ref
v d
v ol ) i sd
i ss where: c ss is the soft?start timing capacitor; v ref is the internal reference voltage, 5.0 v typical; v d is the internal diode forward voltage on between the reference voltage and ss/dmax pin in ic internal, is 0.6 v typical; v ol is the overload threshold voltage. refer to figure 39 overload detection block diagram, the overload threshold voltage is 0.5 v typical;
ncp1212 http://onsemi.com 17 i sd ?i ss is the internal current source for c ss discharging, 20 a typical. the discharging time for 0.22 f soft?start capacitor is: t dis 0.22 f (5.0 v
0.6 v
0.5 v) 20 a 42.9 ms the discharging waveform on ss/dmax pin is shown in figure 41. the discharging time from 4.0 v to 0.6 v is measured as 36 ms from figure 41. by interpolation, discharging time can be estimated as about 41.3 ms when output is overload which agreed with the calculated result. figure 41. ss/dmax pin discharging waveform 36 ms 3.4 v 2. determine the pwm switching frequency the switching waveform is generated by the action of charging and discharging by internal current sources to a capacitor connected at c t , pin 4. the relationship of the switching frequency and the value of c t is governed by the equation below: f sw i chg d c t (v th
1) where: i chg is the charging current to c t , 278 a typical; d is the selected maximum duty cycle, 48% or 82%; c t is the capacitor connected to c t pin; v th is the threshold voltage for different maximum duty cycle selection, 2.5 v for 48% maximum duty cycle and 3.8 v for 82% maximum duty cycle. the switching frequency against c t is shown in figure 31 to help the designers to determine the capacitance for their selected switching frequency. 3. determine the bok thresholds brownout detect thresholds are determined by a resistors network that monitors part of the bulk capacitor voltage at bok pin. equations below illustrate the calculation of the resistors value for the network. r upper r lower (v bulk_h
v bulk_l ) 45 a r lower [1.21 v(v bulk_h
v bulk_l )] (45 a v bulk_h ) where v bulk_h and v bulk_l are the desired upper and lower bulk capacitor voltage for brownout detection. assume v bulk_h = 212 vdc and v bulk_l = 186 vdc, select 3.3 k for r lower then r upper can be calculated to be 576 k .
ncp1212 http://onsemi.com 18 figure 42. brownout detect waveforms channel 1: the mosfet?s v ds switching waveform channel 2: primary bulk capacitor voltage channel 3: bok pin voltage experimental results for the brownout action were shown in figure 42. from the captured waveforms, it can be noted that the brownout input threshold voltage is 1.21 v and brownout hysteresis voltage is 1.36 v at bok pin. 4. improving light load and no load regulation for high power applications for high power applications, limited by the dynamic range of the control circuitry, i.e. the control feedback is limited by the swing of the optocoupler. when v fb reaches about 0.1 v at light load conditions, it no longer has the means to further reduce that voltage because of the saturation of the optocoupler. at light load or no load conditions, the primary current is very small and as the current sensing resistor is also small for high power applications, the current sense feedback voltage will be much smaller than 0.1 v. consequently, the control will force to acquire maximum duty cycle operation and the output will increase without control. in order to improve the poor regulation at light load, a small circuit is added as shown in figure 43. with the additional circuitry, when v fb falls below 0.1 v, q2 will drive additional offset current to cs pin and modify the current sensing voltage, v cs . for v fb higher than 0.1 v at normal load operation, q2 will be turned off due to limited v be .
ncp1212 http://onsemi.com 19 figure 43. suggested solution for better light load regulation fb +5 v 3 r r 2 4 3 9 k 1 300 ns leb s q q current limit + ? output + ? output + ? 1 v osc block reset set r f/f outp ut cs 1 2 3 4 r2 100 3 k 0.1 q2 pnp vcc r8 2.5 k q1 pnp totem pole driver the skip mode operation waveform at light load is shown in figure 44. where channel 1 is the gate drive pin waveform and channel 2 is the cs input pin waveform. figure 44. skip mode switching waveform at light load
ncp1212 http://onsemi.com 20 package dimensions soic?8 d suffix case 751?07 issue ag seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
ncp1212 http://onsemi.com 21 package dimensions pdip?8 n suffix case 626?05 issue l notes: 1. dimension l to center of lead when formed parallel. 2. package contour optional (round or square corners). 3. dimensioning and tolerancing per ansi y14.5m, 1982. 14 5 8 f note 2 ?a? ?b? ?t? seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max min max inches millimeters a 9.40 10.16 0.370 0.400 b 6.10 6.60 0.240 0.260 c 3.94 4.45 0.155 0.175 d 0.38 0.51 0.015 0.020 f 1.02 1.78 0.040 0.070 g 2.54 bsc 0.100 bsc h 0.76 1.27 0.030 0.050 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m ??? 10 ??? 10 n 0.76 1.01 0.030 0.040
ncp1212 http://onsemi.com 22 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 ncp1212/d the product described herein (ncp1212), may be covered by one or more of the following u.s. patents: 6,385,060, 6,385,061, and 6,271,735. there may be other patents pending. literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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